[Scrap] Single-Electron Transistors

December 8, 2014

Single-Electron Transistors

A Whole New Way of Switching

by Bryon Moyer

I love surprises like this. You go into what promises to be a wonky, even dull, conference presentation – and come out agog.

That’s exactly what happened to me at the recent ICCAD in San Jose. It was a presentation based on a collaboration between the University of Michigan, Shanghai Jiao Tong University, and National Tsing Hua University about some placement or routing algorithm, but it happened to involve a transistor type that I’d never heard of. And… I don’t know, there was something about the regularity of it, perhaps its elegance, illuminated through a very lucid presentation, that caught my fancy. Heck, even with no prior knowledge, I could actually follow most of the talk. That was exciting enough. Great success!

So… what was this thing? It was a way of implementing logic on a fabric of single-electron transistors (SETs). In fact, a reconfigurable fabric. This could be your new FPGA some years hence. But, while I could follow the logic of the presentation, I had no idea what a SET was, nor did I understand why certain constraints existed that affected the algorithms presented.

So, having plowed through the interwebs for more information, I decided to split this story into two. First we’ll discuss the underlying semiconductor technology. That will pave the way for a discussion of the EDA implications in a separate article to be published shortly. There are a fair number of places from which to piece together information on some of these concepts, but I found two papers particularly illustrative. One is the ICCAD paper just mentioned; the other is a paper from Penn State on the actual fabric. Links to both follow at the bottom.

A Quantum of Current

First off, we’re talking about a tiny transistor featuring the tiniest of currents. Great for ultra-low power and low voltages, but it puts us into the weird, spooky world of quantum. In particular, we’re dealing with a current that’s as low as physically possible – so low that it’s quantized.

How could it be quantized? Because you can’t get a lower current than moving a single electron. This is done through a tunnel barrier and involves a phenomenon called “Coulomb blocking.” As I was reading about it, it struck me as surprisingly familiar – there are ways in which it brings Fowler-Nordheim tunneling (of EEPROM fame) to mind.

The idea is to isolate a quantum dot. A quantum dot is a zero-dimensional “point” – having lost a dimension from the one-dimensional quantum wire, which loses a dimension from the 2-D quantum well, which itself is a dimension short of 3-D bulk material in which quantization goes away.

The dot is, of course, of finite dimensions; it’s not an actual infinitesimal point. But it’s constricted enough to limit severely the number of states available for hosting electrons. By applying a potential, you can move a single electron over into an unoccupied state that’s at a lower energy (thanks to the applied voltage).

But once that electron moves, the state is full (assuming the potential made only one such state available). Looked at differently, the electron now opposes the applied potential, so a yet higher potential is needed to move yet another electron. This self-limiting nature was specifically what reminded me of Fowler-Nordheim tunneling, where the accumulating electrons on a floating gate oppose the voltage that got them there. Kind of like folks moving into a new neighborhood and then trying to pass ordinances making it hard for others to move in.

SETs are built using quantum wires (also called nanowires); no ordinary wires these, they have quantized conductance due to the confinement of the wire. More on how these are arranged in a minute. For now, let’s concentrate on the transistor itself.

Tunneling Transistors

A SET looks a lot like an MOS transistor. It consists of a drain, an “island,” and a source, all separated by tunnel barriers. Control is provided by a gate – no current tunnels to or from the gate.

 

That island is the quantum dot, and the gate controls the potentials that allow or disallow current. I’m not going to get into the details of how this works because it immediately dives into the infernal world of quantum wave functions, which are nice and all, but they suck all the life from quantum – at least for me. OK, ok, you need the math to do anything useful, but this isn’t a how-to, so we’re moving on.

The way this transistor is implemented starts with the concept of the wrapped-gate nanowire; let’s address the nanowire part of that first. A nanowire isn’t simply a small wire; it needs proper confinement. These guys built that by creating a “heterostructure” consisting of an InGaAs layer sandwiched between two InAlAs layers. The middle layer is the conductor, and the layers above and below it provide the confinement to one dimension. The “pyramidal” (sort of) cross section of the wire comes about due to crystal orientation; a bit more on that later.

 

A further step is then taken to provide the one more element of confinement needed to get a zero-dimensional quantum dot. This is done using “wrapped” gates – two of them, between which a dot can be formed. In the simplest implementation, both gates originate as a “split” from a single gate signal.

 

These wrapped gates aren’t the “gate” shown in the first drawing: they’re a means of taking a nanowire and creating – or removing – a quantum dot (we’ll get to the other gate – the “control gate” – in a minute). As originally implemented, each gate wraps three sides of the nanowire. By adjusting the potential on the gate, you create depletion regions by virtue of a Schottky contact with the nanowire, and the extent of those regions defines how this operates.

With a high voltage, no depletion region exists, and the nanowire acts like… a nanowire. If you apply a very negative potential, two depletion regions will form and overlap, blocking all conduction. Somewhere between those extremes, the depletion regions will create limited barriers, with a space between them. The regions themselves are then the tunnel barriers, and the space between is the quantum dot. In this state, the transistor is said to be “active.” This literally means that, during operation, transistors can be created or removed in real time.

 

The control gate – this is the gate that acts like the MOSFET gate – is then added on the top. So you have the two wrapped gates in close contact with – and therefore with strong influence on– the nanowire, and you have the control gate that also has strong influence (although slightly less so) by virtue of a high-κ dielectric.

 

In the image above, I’ve made an assumption, since there are only so many of the fabrication details that I’m aware of, and I don’t want to get completely lost in minutiae. But, just as you’d want high-κ for coupling the control gate to the quantum dot, so you’d want to make sure the control gate doesn’t couple to the wrapped gates. As shown (which is similar to a drawing in the paper), that would suggest a low-κ material there. I could be wrong… but then again, this is but a way-station. We’re not stopping with this configuration.

A Non-Volatile Device

So far so good. But the Penn State folks have taken things one step further. Rather than splitting a single gate, they’ve made the lines independent. They did this by removing the full wrap, relying entirely on one sidewall for contact. They claim this as a critical part of their proposed structure. (Note that the low-κ question is now moot.)

 

Note that the depletion regions would now emanate from one side only. Presumably this would have some effect on the actual potentials used for the active and open states.

 

They’ve then added non-volatile storage. One way of doing this is to use a ferro-electric material – analogous to a magnet that can be repolarized, except that it’s an electric dipole rather than a magnetic one. You may be familiar with them as used in FRAMs. It’s inserted between the now-unwrapped gate and the nanowire.

 

This material now forms the Schottky contact; the erstwhile wrapped gate no longer touches the nanowire directly.

This means that the wrapped gate lines, rather than being real-time arbiters of the transistor configuration, now become part of the programming infrastructure, and a non-volatile cell is programmed to create (or not) the depletion regions that determine how the device operates.

Here again there are details I’m not sure about. Like how such a material would be deposited, and whether the way I’ve drawn it would reflect an “as-built” configuration. It may be a conceptual view only, or perhaps a configuration for small-scale labs. But it should serve our purpose for the nonce.

I think it’s worth pausing a moment to reflect on this: if this all works as advertised, then you can create a fabric out of this stuff and program it to implement any logic. How that works, we’re coming to next. But you’ll notice that this involves no SRAM bits for storing state, there’s no external non-volatile memory keeping track of things while we’re powered down. A “simple” layer of non-volatile storage material sandwiched in there lets us set and maintain the configuration whether powered up or not. Of course, it takes some infrastructure to do the programming… we’ll come back to that.

All details aside, this seems pretty cool to your intrepid reporter.

A Hexagonal Fabric

Let’s move on to how we connect these things to do something useful. This isn’t going to be your usual configuration of gates driving other gates: there simply isn’t enough drive current to do that. So a completely different approach is used.

Other work (also linked below) shows how you can use selective etching to create a hexagonal array of nanowires. The selectivity comes along crystal boundaries, and it drives the hexagonal angles in the horizontal plane. It also gives the pyramidal structure of the nanowires. That particular paper uses GaAs sandwiched between AlGaAs, but the concept is similar to the version we described above.

The way such a hexagonal array works is as follows:

• Each “vertical” line remains a short; it has no SET.
• The angled lines are outfitted with the gates necessary to make a SET.
• Along each horizontal row of angled lines, crossing all hexagons, one variable drives all the control gates (a and b and the dashed lines in the drawing below).
• From each vertical line, you get an angled line going down to the left and one going down and to the right. One represents the “true” version of the control variable for that SET; the other represents the complement (or "false" version). Which is which is something we’ll come back to; one implementation is shown below.

 

This figure uses a particular arrangement where the line coming down and to the left represents the true value of the control variable; the line coming down to the right side represents the false value. The way we perform logic is to have a “top” of this network where we “insert” current (even though the electrons are actually inserted from the bottom) and then configure these SETs to pass or block the current according to the control variables.

This is where the programming of the SETs is critical. If a logic function needs the negative value of a variable, then the corresponding active low SET is programmed to the active state – and the SET on the active high side is programmed to block current.

The following figure shows the simple example implementing the function “f=ab̅” in a fabric having control gates for variables a, b, and c. Variable c doesn’t figure into this function, so those SETs could be configured as shorts (for simplicity in this view). The SETs for the unused polarities of a and b are configured as opens; they never conduct. So the only way current can flow is when a is 1 and b is 0 (using active high logic). The practical assumption is that there is a current detector at the bottom or top that will determine whether or not a current has passed.

 

Because these networks get complicated for more serious logic, some notational shortcuts have been adopted, so you’ll mostly see networks that would make the function above look as follows:

 

Note the different line characteristics as well as the fact that each node is labeled with its variable. a1 and a2 both represent variable a, and they can’t take on different values of a, but they represent two different decision points.  This becomes more useful for EDA algorithms assigning logic to nodes.

Note also that in the case of node c1, I’ve shown it as short, but, as indicated, it could also be open. If other nodes from b came in from the left (the gray dashed line), for example, then you’d probably want to cut off that path so that it didn’t represent a sneak path that messed up the evaluation of the function involving only a and b. (Then again, that dashed line could also be configured as an open, blocking current there…)

Spoiler alert for the next article: this arrangement looks strikingly similar to a binary decision diagram (BDD). That’s no accident. More about that in the EDA follow-up, when we’ll make yet more simplifications to the fabric drawings.

Fabrics and Constraints

Ok, we’re almost there. Two important considerations remain. First, I mentioned the question of whether the active high or low states branch to the left or right. That’s a fabric design decision. What we show in the above figures has active high going to the left and active low going to the right; this is referred to as a “symmetric” fabric. But it doesn’t have to be that way.

A “mirror” fabric would reverse the directions at every node. Then there are “sparse” fabrics that are mostly one way, with the occasional reversal.

 

Why these options? Because optimizations sometimes make it useful to share “sub-trees” – parts of the logic useable in common by different functions. Depending on whether these sub-trees are desired in their true or complement form affects how you’d like the fabric to look. There’s no one right answer for every situation.

This question gives rise to a “fabric constraint” that must be met by the placement algorithms. The exact nature of the constraint depends on the organization of the fabric. We’ll see that in action in the follow-up piece.

Finally, there’s the issue of programming infrastructure. A grid of vertical and horizontal wires is needed for x/y addressing to program individual SETs. That gets to be a lot of wires, and so some sharing has been proposed to cut down on the congestion. You could share one wire for two neighboring nodes or for four (or more). The more sharing, the more constraint you place on what can be placed where, since you’ve reduced some degrees of freedom; you can no longer program each node independently of other nodes.

This gives rise to what’s called a “granularity constraint.” The granularity in this case refers to how many nodes are interrelated in this way. The most granular arrangement is for each node to be independent; these optimizations reduce the granularity, and they affect how logic is to be assigned. Again, we’ll see this put to effect in the next article.

OK…That’s it for now. From a collection of a number of simple concepts we get this fabric that’s strikingly simple and seems relatively efficient. Then again, we’re looking at it only from a conceptual standpoint. This isn’t necessarily an ivory-tower exercise, since some of the manufacturing considerations have been studied. But we’ve pretty much ignored manufacturing, and there are probably potential issues that are not even known yet. So in case it’s not obvious, this is still a research topic.

There is one clear limitation in what we’ve seen: this is purely a combinatorial fabric. There’s no intrinsic way to route feedback for flip-flops (nor was any raised in the papers I’ve read). Presumably such a modification would involve taking the results from the detectors and routing them to variables (the horizontal lines controlling the control gates). Let’s leave that as an exercise to be sorted out by the researchers.

Next up: how you take logic and implement it on this fabric. Which was the topic of the ICCAD paper that started this whole thing. We just couldn’t get there without first addressing the basics.

More info:

Reconfigurable BDD-Based Quantum Circuits

BDD-based synthesis of reconfigurable single-electron transistor arrays (behind paywall)

Hexagonal fabric: I have a paper that I can no longer find except behind paywalls. If you search, you may also find an open copy. Here is an open abstract of the work:https://www.electrochem.org/dl/ma/206/pdfs/1039.pdf

Formation of High-Density GaAs Hexagonal Nano-wire Networks by Selective MBE Growth on Pre-patterned (001) Substrates (behind paywall)

January 19, 2015

EDA for SETs

A Flavor of Single-Electron Transistor Algorithms

by Bryon Moyer

A few weeks back, we tackled the concept of a single-electron transistor (SET). And we saw how they could be arranged in a hexagonal form for use as a non-volatile programmable fabric. The whole topic originated for me in an ICCAD paper that discussed EDA algorithms for implementing logic in such a device. Well, before discussing that, we needed to introduce SETs. So, having done that, we now return to the originating topic: how do you take random logic and implement it in a SET fabric?

This could descend into the realm of intricate minutiae (details make the difference between algorithms that work and ones that almost work); I’m going to delve in only so far for flavor. I’ll refer you to the original paper (link at end) for the remaining bits. But… yeah, it’s gonna get moderately wonky.

It’s also important to keep in mind that what we will discuss is only combinatorial logic. It’s early days for SETs – they’re far from commercialization, so full system implementation is a ways away yet. I checked in with all of the major EDA guys – no one is working on this in any serious way. It’s still considered to be too researchy.

So why even put time into it now on these pages? I guess because it fired my imagination; it seemed different enough from what we’re used to that it was nice to spin up a whole new section of my brain to think about this. Hopefully it does for you too.

SET review

So… as a quick review, let’s reprise a couple of quick relevant notes; I’ll refer you to the prior article for a better understanding of the underlying whys and wherefores.

• A SET allows one electron to pass from source to drain if the gate so directs.
• SETs can be arranged into a hexagonal fabric such that a single electron can be routed from one end of the fabric all the way through to the other end.
• Each horizontal row along the “angled” hexagon facets corresponds to a single variable. The SET on one branch reflects the “true” value test; the SET on the other branch reflects the “false” test. Vertical lines are shorts.

 

• A function qualifies as “true” (assuming active-high logic) if an electron can find a path through the fabric.

 

• A simplified graphic notation is used (which we will simplify yet further for algorithmic purposes). It’s slightly more efficient than the figures above. The following figure is equivalent to the prior one. The numbers on the variables (a1, a2, etc.) serve only to identify specific nodes in the fabric; they’re not different variables.

 

The graphic simplification we will make gets rid of the shorts that are always shorts: the vertical lines. The resulting diagram looks like diamonds more than hexagons and is therefore less reflective of the physical arrangement, but the abstraction allows more focus on what matters. Here again, the following figure is equivalent to the prior one.

 

Finally, we talked about a couple of constraints (granularity and fabric) last time; we’ll return to those, but there’s one even more fundamental constraint that we didn’t discuss: when the fabric configuration is complete, it’s important that one, and only one, path through the fabric be activated at any given time.

That’s because we’re talking about incredibly small currents that need to be detected – the smallest current possible, to be specific: a single electron. Having multiple paths active will completely muddy that measurement up, so it’s not allowed.

First constraints: one true path and planar

Ok, with those preliminaries out of the way, let’s look at how you implement logic on one of these puppies. As noted, this arrangement looks suspiciously like a binary decision diagram (BDD). At each level, we’re making a true/false decision and moving either to the left or to the right. BDDs will be pretty familiar to EDA types; they’re less so for the rest of us (hence the basics here).

BDDs tend to get simplified to “reduced order” BDDs (ROBDDs). This process, to me, is akin to going from a canonical sum-of-products (SoP) Boolean form to a minimized Boolean form. They’re equivalent, but one is more efficient – if more ad hoc in form.

So, for example, the following BDD can be simplified to the equivalent ROBDD by dropping variable nodes that don’t actually do anything (like b2 and c2) and merging nodes where possible (d1 and d2).

  

The original BDD looks a lot like the SET fabric situation, but there’s a critical difference: a BDD doesn’t have to be planar. In other words, it can have lines that cross each other – something that’s not possible in a SET fabric. An example of part of a non-planar BDD, shown in the paper, looks as follows:

 

Because a BDD (or ROBDD) has this fundamental difference from SET fabrics, early algorithms transformed the BDD into sums of products and then worked from the textual product terms to find a mapping on the SET fabric.

But the Michigan/Shanghai Jiao Tong/Tsing Hua team noted that, by moving from the graphic BDD to the SoP form, you sacrifice useful structural information inherent in the BDD. So their approach is to transform the ROBDD into a planar BDD that can be directly mapped onto the fabric. They abandon the transformation to SoP form entirely. This has resulted in some more efficient implementations.

Ironically, the first steps they have to take on the ROBDD serve to reverse some of the steps that turned the BDD into an ROBDD. Those include:

• Pruning 0 nodes and associated edges, focusing only on true- or 1-oriented logic (the rest remaining implicit).
• Repopulating all variables; where true and false decisions have the same destination, turn that into a short.
• Merging identical nodes (they have to be identical for all logic below).

These steps are reflected in the next figure.

 

But what about non-planar BDDs? This results in some logic replication. So, taking the non-planar example from further up, you have to duplicate the destination node that causes the crossing. That means duplicating any downstream logic too.

 

If you can place identical nodes next to each other, then they can be merged. It would be really nice if we could swap a2 and a3 up there so the b1 and b1’ nodes would be next to each other and then could be merged. But that would screw up the a1-b2 line, making it necessary to do different reduplication. So it doesn’t really help here; it can in other cases.

Next comes a step where conflicts are resolved. Mapping may try to place two nodes in the same place. These conflicts are an artifact of the detailed mapping process. If we look at it as humans, we might simply say, “Duh, don’t do that.” Computers have fewer such insights. (Some future work might create a conflict-free mapping that makes this step unnecessary.)

So the following example, from the paper, shows that two logical nodes, c2 and c3, might end up being mapped to the same place. Now… if those nodes were identical – including all downstream logic, this might be efficient. But if not, then this is a no-go. So you have to spread things out to make room so that c2 and c3 can each have their own nodes.

There are a couple of ways of doing this; one involves adding an entire row; the extra row doesn’t do anything except let the conflicting nodes separate. There’s another way to do it if the conflicts happen to occur at the edges of a row; that’s a special case that doesn’t require a new row insertion (I haven’t illustrated this one).

 

Remaining constraints: fabric and granularity

So at this point, we’ve transformed the ROBDD into a planar BDD, and we’ve met the two most important constraints: one true path and planar. Now we need to address the two remaining constraints: fabric and granularity. Frankly, these get more intricate than I really want to tackle here, but let’s review why these are necessary and then abstract how it’s solved.

In this piece, we haven’t been paying attention to whether “true” branches come out to the left or right. Mostly we’ve had true out to the left and false out to the right, but that’s probably biased by BDD convention. In reality, up to this point, there’s nothing to stop us putting any branch in any direction. That’s particularly useful if two nodes – one the outcome of a true test, the other of a false test – share the same resulting node.

But the underlying SET fabric places limitations on this. It’s a specific result of fabric design decisions as to which lines to connect to the true version of a variable and which to the false version. As we saw last time, there’s the standard “symmetric” version, with all nodes the same; there’s the “mirror” version, where the arrangement reverses in between; and there’s any other combination you want. The algorithm in this paper assumes that each row is consistent throughout, but that different rows can have different arrangements.

 

So, if we have a symmetric fabric, then the convenient arrangement on the left below will not work. It’s nice because the node d1 can be shared, but in order for that to happen, the branch from c2, which is a false test, has to go to the left – a no-no with a symmetric fabric. Instead, node d1 (and its follow-on logic cone) must be replicated. This consideration works itself into the mapping algorithm.

 

Finally, there’s the granularity constraint. You may recall that this originates in an attempt to save metal lines. For highest granularity, each decision point – which is to say, each SET – can be programmed to be active or open or short. But that results in a lot of metal lines for programming access, so architects consider sharing nodes – doubling or even quadrupling up. This means that shared nodes have to be programmed alike, which makes some combinations impossible.

So, for example, programming two SETs identically with one line means that the SETs must either both be active (whether true/false or false/true is determined by the fabric), both short, or both open. We can’t have an active-high line coming out the left and an open coming out the right, for example.

While the fabric constraint becomes part of the mapping algorithm, the granularity constraint is handled as a modification after the initial mapping to expand or fluff out the network, allowing only legal combinations. From the example below, given by the authors, this seems to chew up quite a bit more fabric than would be necessary without the constraint; that’s the price paid for the more efficient programming infrastructure.

In this example, you can see the illegal combination (red on the left); in the expanded network, the original logic lines are shown in green. All other lines are there simply because they have to be, due to the constraint (as indicated by the maroon markings).

 

For instance, in the node between a1 and b1, there’s a false branch that then goes to a node with two opens. In other words, it does nothing. But because the left branch is active, the right branch has to be as well – and so the following open branches ensure that the unneeded false signal goes nowhere.

OK, that’s it, I promise. Wait, where did everyone go? Come on… this isn’t that dull, is it? I guess for me, this makes up for all the times I saw crazy-assed quantum math and freaked out. This is my kind of math.

So let’s pull ourselves up out of the muck and take stock. The intent here is to give a flavor of what EDA tools will be required to do if or when SETs ever become a thing. Specifically, if they become a thing in programmable fabrics like this. (Who knows, they might become manifest in a completely different arrangement.)

And… this is likely to be the last you see of SETs for a long time. Yeah, maybe not something you’ll be using next week, but consider this a flight of fancy into what logic might someday look like.

We now return you to stuff that matters next week.

More info:

BDD-Based Synthesis of Reconfigurable Single-Electron Transistor Arrays (behind a paywall)