[Scrap] Optimising BGA signal routing in PCB designs

Optimising BGA signal routing in PCB designs

Posted:02 Feb 2015

Ball grid array (BGA) device packaging is today's standard for housing a range of highly advanced and complex semiconductor devices such as FPGAs and microprocessors. The technology of BGA packaging for embedded designs is steadily advancing to keep up with chipmaker technical advances, with this type of packaging splintering out into standard and micro BGAs. Today, both types deal with increasing numbers of I/Os, and this means signal escape routing is difficult and challenging, even for experienced printed circuit board (PCB) and embedded designers.

The top job for the embedded designer is to develop appropriate fan-out strategies that won't adversely affect board fabrication. There are several major considerations involved in selecting the correct fan-out/routing strategy: ball pitch, land diameter, number of I/O pins, via types, pad size, trace width and spacing, and the number of layers required to escape the BGA.

PCB and embedded designers will always be challenged to use the minimum number of board layers. The number of layers needs to be optimised to reduce cost. But sometimes a designer must rely on a certain number, for example, to suppress noise by sandwiching actual routing layers between ground plane layers.

Figure 1: Dog bone fan-out.

Aside from those design factors inherent in particular BGA-based embedded designs, a major portion of the design involves two basic methods the embedded designer has to perform to correctly escape signal traces from a BGA: dog bone fan-out (figure 1) and via-in-pad (figure 2). Dog bone fan-out is used for BGAs with 0.5mm (mm) and above ball pitch, while via-in-pad is used for BGAs and micro BGAs with below 0.5 mm ball pitch, also known as ultra-fine pitch. Pitch is defined as the spacing between the centre of one BGA ball to the centre of the next one.

Figure 2: Via in pad fan-out.

It's important to know some basic terminology associated with these BGA signal routing techniques. The term "via" is the most prominent. It refers to a pad with a plated hole connecting copper tracks from one PCB layer to other layers. High-density multi-layer boards may have either blind or buried vias, also known as micro-vias. Blind vias are visible only on one surface; buried vias are visible on neither surface.

Dog bone fan-out 
Dog bone BGA fan-out provides partitioning into four quadrants with a wider channel in the middle of the BGA to run multiple traces from inside. Several key steps are involved to break out signals from the BGA and connect them to other circuitry.

The first step is to determine the via size needed for the BGA fan-out. Via size depends on a number of factors—device pitch, PCB thickness, and the number of traces to be routed from one area of the via or one perimeter to the next. Figure 3 shows three different perimeters associated with a BGA. A perimeter is the boundary of a polygon is defined in a shape of a rectangle or square surrounding the BGA balls.

Figure 3: Three different perimeters associated with a BGA.

Consider an imaginary line going through the first row (horizontally) and first corresponding column (vertically) comprising the first perimeter, and again for the second and third perimeter. A designer starts off routing the outer perimeter of the BGA, then moving inward, and, in the end, towards the inner-most perimeter of the BGA balls. Via size is calculated using land diameter and ball pitch, as shown in table 1. The land diameter is the diameter of the pad of each BGA ball.

Once the dog-bone fan-out is done and the particular via pad size is determined, step two is to define trace width for traces coming into the board's internal layers from the BGA. A number of factors go into confirming trace width. Table 1 shows that trace width. Minimum space required between traces define a BGA's escape routing. It's important to know that reducing spacing between traces increases board fabrication cost.

The area between two vias is called a channel for running the traces. The channel area between adjacent via pads is the smallest area through which the signal must be routed. The number of traces that can be routed through this area is calculated using table 1.

Table 1: Calculating via size using land diameter and ball patch.

As table 1 shows, performing BGA signal escape routing is defined by trace width and the minimum space required between traces. The channel area between adjacent via pads is the smallest area through which the signal must be routed.

Channel area CA= BGA pitch—d, where d is the via pad diameter.

The number of traces that can be routed through this area is calculated using table 2.

Table 2: Calculating the number of traces through a given channel area.

A number of traces can be routed through various channels. For example, one or two traces can be routed and sometimes three if BGA pitch isn't very fine. For instance, with a one-millimeter pitch BGA, multiple traces can be routed. However, with today's advanced PCB designs, most often only a single trace is routed through a channel.

Once the embedded designer has determined trace and space width, the number of traces routed through one channel, and type of via to be used for the BGA layout, he or she can estimate the number of layers that will be required. Use of fewer I/O pins than the maximum can reduce the number of layers. If routing on primary and secondary side is allowed, then the two outer perimeters can be routed without using vias. The next two perimeters can be routed on the bottom side.

At step three, the designer keeps impedance matching as required and determines the number of routing layers to be used to completely breakout the signals from the BGA. Next, he or she routes the BGA's outer periphery using the top board layer or the same layer where the BGA is placed.

The remaining inner parameters are distributed among internal routing layers. Depending on the number of traces routed internally within each channel, a fair estimate is made on the number of layers required to completely route the BGA.

Once the outer periphery is routed, the next periphery is routed. The set of images in figure 4a andfigure 4b illustrate how a PCB designer routes different BGA peripheries, starting from the outermost and moving to the centre. The first image shows how the first and second inner periphery is routed. Subsequent internal peripheries are similarly routed until the BGA is completely routed.

Figure 4a and 4b: How to route different BGA peripheries, starting from the outer most and moving to the centre.

In some designs where electro-magnetic interference (EMI) is a concern, the external layer or top layers aren't used to route even the outer periphery. In that case the top layer is used for a ground plane. EMI includes the susceptibility of a product to fields from the outside world that couple in and radiate emissions from a product, which causes it to fail compliance tests. A product is considered EMC compliant if it satisfies three criteria: 
 • It doesn't interfere with other systems
 • It's not susceptible to emission from other systems
 • It doesn't cause interference with itself.

To prevent the product from transmitting and receiving undesired signals, it's recommended that the product be shielded. Shielding generally refers to a metallic enclosure that completely encloses an electronic product or portion of product. However, in most cases having the outer layers filled with ground plane serves the shielding purpose as it absorbs energy and minimises interference.

Via in pad for ultra-fine pitch 
When using the via-in-pad technique for BGA signal escape and routing, vias are placed directly on the BGA pads and filled with conductive material, usually silver, that provides a flat surface.

The micro BGA via in pad fan-out example used here is based on 0.4 mm ball or lead pitch and the PCB is 18 layers, including eight signal routing layers. A greater number of layers is usually required for BGA routing. But in this example, the number of layers isn't an issue since fewer number of BGA balls are involved. Still, the key issue is the micro BGA's narrow pitch of 0.4mm with routing not permitted on the top layer, except for fan-outs. The goal is to fan out the micro BGA without adversely affecting PCB fabrication.

Figure 5 shows the footprint from the BGA device's manufacturer. As can be seen, the recommended pad size is 0.3 mm (12 mils), and pin pitch is 0.4 mm (16 mils). It's not possible to have the traditional dog bone fan-out pattern due to the extremely small space between the pads. Even a small size via cannot be used for a dog bone fan-out strategy; here a small size via means 6 mil drill and 10 mil annular pad. Another important mechanical limitation is board thickness, which is 93mils.

Figure 5: Footprint from the BGA device's manufacturer.

In this case, the easiest solution is using micro-via-in-pad. However, micro-via size cannot be more than 3 mils. But the 93 mils board thickness is a limiting factor. Another option is blind and buried via technology. These options will limit manufacturing choices and increase costs.

To have the option of going to different fabrication houses, drill size in a 93 mils thick board cannot go smaller than 6 mils, and trace width cannot be smaller than 4 mils. Otherwise, only a high end, exclusive board manufacturer can handle this project, at a premium. Figure 6 shows the BGA footprint associated with this example.

Figure 6: This fan-out method avoids using a high-end technique and doesn't jeopardise signal integrity. BGA pins are divided into two sections as far as internal and external pins.

The fan-out method shown in figure 6 avoids using a high-end technique and doesn't jeopardise signal integrity. BGA pins are divided into two sections as far as internal and external pins. Via-in-pad is used for the internal section, while external pins are fan-out at a 0.5mm grid. Figure 7a shows the top layer and figure 7b shows top and internal routing layers.

Figure 7a and 7b: Via-in-pad is used for the internal section, while external pins are fanned out at a 0.5mm grid. Fig. 7a shows the top layer; Fig. 7b shows top and internal routing layers.

Since BGA pad size is 0.3mm (12mils) and pitch is 0.4mm (16mils), a 6/10mil via (hole/annular ring size) is used in the pads. The same via is used for external extended fan-out. For the internal section, clearance between vias is 6 mils, which is standard and doesn't pose a problem at fabrication. For the external section, spacing between vias is 10 mils. This spacing is used to run a 3-mil trace with a 3.34-mil distance from the vias. This particular strategy allows all signals from a 0.4mm pitch micro BGA to be successfully fanned out without complying with any special fabrication requirements.

The basic steps remain the same whether using dog bone or via in pad, i.e. defining proper channel space. It includes defining via hole and pad size, trace width, impedance requirements and stackup. However the difference lies in via arrangement and the sets of vias that are used.

It is recommended that a blind/ buried via configuration up to six layers in depth be used. Going beyond causes fabrication yield issues. The preferred technique is to use staggered vias vs. stacked vias, as shown in figure 8. Staggered vias allow for more accurate registration tolerance as they're not mandated to align perfectly as required in the case of stacked vias.

Figure 8: Staggered vias allow for more registration tolerance, as they're not mandated to align perfectly as required in the case of stacked vias. (Courtesy of IPC).

What can go wrong by missing these steps

Manufacturing and functionality are two key aspects that need to be considered regardless of whether dog bone or via in pad is used. It's critical to know the manufacturing limits of the fab shop that will be used. There are shops that can manufacture extremely tight designs. However, if the product is going to volume production it gets very costly. It is therefore extremely important to design in a way that average manufacturing facilities can handle them.

To summarise, the key factors to consider from manufacturing perspective are
 • Stack-up
 • Via—hole size (depends on aspect ratio)
 • Via—annular ring (min 3 mils is required)
 • Via—stacking (stacked vs staggered)
 • Copper to copper space. (min 3 mil is recommended)
 • Copper to drill space. (min 5 mil is required)
 • BGA land size vs ball size for assembly.

There is always a trade-off when it comes to manufacturability vs functionality. It is critical to analyse each properly and make calculated decisions.

Functionality, on the other hand, includes signal integrity, power distribution, and EMC. These can be divided into several main categories: 
 • Reflection and transmission line (one line) Key is impedance control. Impedance is controlled by trace width, dielectric thickness and reference plane.
 • Cross talk (two or more lines) Spacing between traces on same and adjacent layer is key to control cross talk. Having ground layers between each signal layer, and ground shield traces around noise sensitive or noise emitting traces help minimise cross talk.
 • Power distribution (rail collapse) This is inductance of power nets. Having power and ground planes adjacent and decoupling caps helps control power surges.
 • EMI (system collapse) The controlling of all above elements and shielding the entire PCB or noise sensitive and generating portion helps control EMI.

This is true for the entire product. However, this is particularly true at BGA areas where all signal and power come in close proximity to each other, thus making it challenging. Proper knowledge of signal characteristics help in making decisions as to which net has more priority in terms of functionality.

Having a solid ground plane in a layer adjacent to the BGA helps in tackling most signal integrity concerns. One critical benefit of blind vias is that the stub length is eliminated in blind/buried vias, and this is extremely important for high frequency signals.

Conclusion
The technology of BGA packaging for embedded designs is steadily advancing, but signal escape routing is difficult and challenging. Several major considerations are involved in selecting the correct fan-out/routing strategy: ball pitch, land diameter, number of I/O pins, via types, pad size, trace width and spacing, and stackup. Following the strategies outlined in this article ensures that a product is correct in terms of form, fit and function.

About the authors
Faisal Ahmed is a PCB layout engineer at NexLogic Technologies, Inc., San Jose, CA. His design and layout experience spans 14 years, with emphasis on mixed signal and HDI. He received his BS degree in Electronics from NED University of Engineering and Technology Karachi Pakistan.

Ishtiaq Safdar is a PCB layout engineer at NexLogic Technologies, Inc., San Jose, CA. He has been a board design and layout engineer for more than 10 years. He has extensive experience working on PCB designs populated with small packaging to include micro BGAs. He received his Bachelor of Engineering (BE) in industrial electronics from NED University of Engineering and Technology, Karachi, Pakistan.

This article was printed from EE Times-Asia located at::
http://www.eetasia.com/ART_8800709341_480200_TA_b4d2a058.HTM